Fabrication of 4H-SiC lateral double implanted MOSFET on an on-axis semi-insulating substrate without using epi-layer

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Abstract

© 2017 The Japan Society of Applied Physics. 4H-SiC lateral double implanted metal-oxide-semiconductor field effect transistors (LDIMOSFET) were fabricated on on-axis semi-insulating SiC substrates without using an epi-layer. The LDIMOSFET adopted a current path layer (CPL), which was formed by ion-implantation. The CPL works as a drift region between gate and drain. By using on-axis semi-insulating substrate and optimized CPL parameters, breakdown voltage (BV) of 1093 V and specific on-resistance (R on,sp ) of 89.8 mΩ•cm 2 were obtained in devices with 20m long CPL. Experimentally extracted field-effect channel mobility was 21.7 cm 2 •V -1 •s -1 and the figure-of-merit (BV 2 /R on,sp ) was 13.3 MW/cm 2 .

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Kim, H. W., Seok, O., Moon, J. H., Bahng, W., & Jo, J. (2017). Fabrication of 4H-SiC lateral double implanted MOSFET on an on-axis semi-insulating substrate without using epi-layer. Japanese Journal of Applied Physics, 56(12). https://doi.org/10.7567/JJAP.56.120305

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