HKMG CMOS technology qualification: The PBTI reliability challenge

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Abstract

We present a brief overview of Positive Bias Temperature Instability (PBTI) commonly observed in n-channel MOSFETs with SiO2/HfO2/TiN dual-layer gate stacks when stressed with positive gate voltage at elevated temperatures. We review the origin and present understanding of the characteristics of oxide traps that are responsible for the complex behavior of threshold voltage stability. We discuss the various physical mechanisms that are believed to govern the transient charging and discharging of these traps as the backbone of the models that have been proposed for PBTI degradation and recovery. Next we review the state-of-The-art in PBTI characterization and we present some of the key stress results on both the device as well the circuit level. Special emphasis is given on the open PBTI issues that need to be carefully addressed for a robust reliability methodology that accurately predicts PBTI lifetimes. Finally we mention some of the gate stack scaling effects on PBTI. © 2014 Elsevier Ltd. All rights.

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APA

Ioannou, D. P. (2014). HKMG CMOS technology qualification: The PBTI reliability challenge. Microelectronics Reliability, 54(8), 1489–1499. https://doi.org/10.1016/j.microrel.2014.03.018

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