Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

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As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.




Qi, C., Xiao, L., Guo, J., & Wang, T. (2015). Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology. Microelectronics Reliability, 55(6), 863–872. https://doi.org/10.1016/j.microrel.2015.03.014

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