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Abstract

This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC with an equivalent number of samples equal to N<sup>2</sup>, at the negligible area cost of doubling the number of minimum load capacitors. The concept is proved in a 65-nm CMOS technology 40MHz TDC, which achieves a 3ps resolution. The differential nonlinearity is reduced from 1LSB to less than 0.2LSB.

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Yaya, R. (2004). Would the objectives and characteristics of Islamic accounting for Islamic business organisation meets the Islamic socio-economic objectives? Jurnal Akuntasi Dan Auditing Indonesia, 8(2), 141–163. https://doi.org/10.1109/ESSCIRC.2010.5619879

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