OpenNoC: An Open-Source NoC Infrastructure for FPGA-Based Hardware Acceleration

Abstract

Network on chip (NoC) architectures enable efficient and scalable interconnection between hardware accelerators on the same chip. Most of the traditional NoC architectures are highly resource intensive and suffer from low clock performance when implemented on field programmable gate array platforms. They fail to provide standard interface to accelerators and fall short on detailing the external interface. Availability of open source NoC infrastructures saves development time also faster adoption of this technique. This letter discusses the implementation of OpenNoC, an open source lite-weight deflection torus-based NoC with PCIe-based communication controller.