Optimization of Underlap Length for DGMOSFET and FinFET

1Citations
Citations of this article
16Readers
Mendeley users who have this article in their library.

Abstract

From the commencement of CMOS scaling, the simple MOSFETs are not up to the performance due to the increased SCEs and leakage current. To slacken the SCEs and leakage currents, different types of structures i.e. Multi-Gate MOSFETs like DG, TG, FinFETs are introduced. Currently the Integrated Device Manufacturer (IDM), foundries and electronic design automation (EDA) companies grant more investments and emphasis on most promising Multi-Gate technology. In this, sensitivity of underlap length on DC and AC parameters like drain current, SS, transition frequency, delay, EDP etc. is studied for both the chosen devices i.e. DG MOSFET and FinFET. From our reported results, DG MOSFET is a good candidate for high current drivability whereas FinFET provides better immunity to leakage currents and hence improved delay, EDP over DG MOSFET. Furthermore, FinFET provides high value of transition frequency which indicates that it is faster than DG MOSFET.

Cite

CITATION STYLE

APA

Singh, D., Pradhan, K. P., Mohapatra, S. K., & Sahu, P. K. (2015). Optimization of Underlap Length for DGMOSFET and FinFET. In Procedia Computer Science (Vol. 57, pp. 448–453). Elsevier. https://doi.org/10.1016/j.procs.2015.07.519

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free