A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

  • Postman J
  • Chiang P
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Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.




Postman, J., & Chiang, P. (2012). A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations. ISRN Electronics, 2012, 1–9. https://doi.org/10.5402/2012/916259

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