Alteration of gate oxides thickness for SOC level integration

  • Sharma S
  • Prasad B
  • Kumar D
 et al. 
  • 2

    Readers

    Mendeley users who have this article in their library.
  • 1

    Citations

    Citations of this article.

Abstract

The integration of entire system on a chip (SOC) is the major challenge for the semiconductor industries. The successful implementation of SOC will require innovation in both circuit design and fabrication technology. However, from a process technology point of view, it can be seen that in order to provide design flexibility each of the sub-system may require different gate oxide thicknesses. In this work, 19F+ implantation of variable doses on silicon is explored to achieve this goal. It has been observed that the differential oxide thickness can be achieved by varying the implanted dose of the fluorine on silicon, due to alteration in the oxidation rate. C-V and J-E characteristics are used to demonstrate the electrical behavior of fluorine implantation-based MOS devices. The stoichiometric composition analysis of dielectric materials is reported by FTIR measurements. The control over the oxide thickness, interface states, threshold voltage and stoichiometric composition of dielectric materials could play a vital role in the SOC level integration. Crown Copyright © 2009.

Author-supplied keywords

  • Alteration oxide thickness
  • C-V
  • Dit and FTIR
  • J-E

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Authors

  • Raj KumarPNG University of Technology

    Follow
  • Satinder K. Sharma

  • B. Prasad

  • Dinesh Kumar

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free