A delay insensitive approach to the VLSI design of a DRAM controller

  • De Gloria A
  • Faraboschi P
  • Olivieri M
  • 2


    Mendeley users who have this article in their library.
  • 1


    Citations of this article.


The paper presents an application of Delay Insensitive VLSI design to a real case. A Dynamic RAM Controller, matching the specification of the Intel 8202®component, has been designed through a delay insensitive methodology, by using a synthesis system developed by the authors. Delay insensitivity is currently a subject of study due to its promising features for VLSI design. Though formal methods have been widely developed, there is a lack of real applications that prove the capabilities of the delay insensitive approach. The main goal of this paper is to show that a delay insensitive methodology is a suitable automated approach to the design of complex VLSI CMOS circuits. © 1993.

Author-supplied keywords

  • DRAM controllers
  • VLSI design
  • delay insensitive circuits
  • self-timed design

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document


  • A. De Gloria

  • Paolo Faraboschi

  • Mauro Olivieri

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free