ESD protection for the tolerant I/O circuits using PESD implantation

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Abstract

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call "PESD" implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance. © 2002 Elsevier Science B.V. All rights reserved.

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Tang, H. T. H., Chen, S. S., Liu, S., Lee, M. T., Liu, C. H., Wang, M. C., & Jeng, M. C. (2002). ESD protection for the tolerant I/O circuits using PESD implantation. Journal of Electrostatics, 54(3–4), 293–300. https://doi.org/10.1016/S0304-3886(01)00157-7

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