ESD protection for the tolerant I/O circuits using PESD implantation

  • Tang H
  • Chen S
  • Liu S
 et al. 
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In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call "PESD" implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance. © 2002 Elsevier Science B.V. All rights reserved.

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  • Howard T.H. Tang

  • S. S. Chen

  • Scott Liu

  • M. T. Lee

  • C. H. Liu

  • M. C. Wang

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