This paper describes the operation and characterization of N-Channel, double-polysilicon gate MOS structures that may be used in an Erasable, Programmable, Read-Only Memory (EPROM). The trade-offs for various structures with regard to writing ability, reading ability, fabrication complexity and ease of erasure are discussed. Measurements of the device are compared to the associated theory, and the sensitivity of the structure to various device parameters is also described. © 1978.
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