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Dean Truong

  • Ph.D., M.S., B.S.
  • Research Scientist
  • Madrigal Elektromotoren GmbH
  • --

    Readers

    Number of times these publications have been added to libraries on Mendeley.
  • 16

    Publications

    Number of items in this person’s My Publications folder on Mendeley.

Research Interests

Hierarchical dynamic power management techniques applied to multiple levels of system integration from the processor to cluster levels using LTI control theory and learning heuristics (e.g. fuzzy logic neural networks genetic algorithms etc.).

Followers (10)

  • Xinfei Guo

    Xinfei Guo University of Virginia

  • krishnamoorthy A

    krishnamoorthy A VIT University Centre for Bio Separation Technology

  • Stanley Cheung

    Stanley Cheung

  • Manishkumar Dudhat

    Manishkumar Dudhat University of Applied Sciences Darmstadt

  • Jon Pimentel

    Jon Pimentel

  • Brian Zimmer

    Brian Zimmer

Explore network

Following (9)

Explore network

About

Natural born U.S. Citizen finishing up a Ph.D. in Electrical and Computer Engineering focusing on the application of dynamic voltage and frequency scaling with a manycore platform architecture for biomedical signal and image processing applications. Goals/Objective: To be part of a state-of-the-art research/engineering group in the areas of embedded systems (e.g. real-time communications and multimedia front/back-end), high performance computing (e.g. Exascale computing), and/or biomedical signal, image, and video processing (e.g. medical ultrasound). Primary Experience: + RESEARCH ASSISTANT with 16 authored and co-authored papers in top circuits journals and conferences, including IEEE Journal of Solid State Circuits, VLSI Symposium on Technology and Circuits, IEEE Transactions on Circuits and Systems, HotChips Symposia on High Performance Processors, and ACM/IEEE Design Automation Conference. + MANYCORE PLATFORM LEAD ARCHITECT working with a team of 10 M.S. and Ph.D. students on a 167-core globally asynchronous and locally synchronous (GALS) array consisting of 164 DSP processors, three application-specific processors (accelerators), and three 16 KB scratchpad shared memories. Design to tape-out completed in 9 months on 65 nm CMOS. The platform is capable of up to 200 GOPS at nominal Vdd, with peak energy-efficiency at 200 GOPS/W at near-threshold operation. Specialties: + Variation-aware Adaptive and Dynamic Voltage and Frequency Scaling (DVFS) on Manycore Platforms + Digital Systems and Computer Architecture + RTL Engineer + Back-end Design and Verification + Digital IC Design + Source-synchronous Interconnects + Lab Instrumentation & Chip Testing + Embedded Software Development + LDPC Decoder Architectures + Medical Ultrasound Imaging on Massively Parallel Processor Arrays (MPPA)

Publications

Massively parallel processor array for mid-/back-end ultrasound signal processing

  • Truong D
  • Baas B
2010 Biomedical Circuits and Systems Conference (BioCAS) (2010)
  • --

    Readers

    Readers not available. This publication is not currently accessible in the Mendeley catalog.
Full text

An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

  • Mohsenin T
  • Truong D
  • Baas B
2009 IEEE International Conference on Communications (2009)
  • --

    Readers

    Readers not available. This publication is not currently accessible in the Mendeley catalog.
Full text

Multi-Split-Row Threshold decoding implementations for LDPC codes

  • Mohsenin T
  • Truong D
  • Baas B
2009 IEEE International Symposium on Circuits and Systems (2009)
  • --

    Readers

    Readers not available. This publication is not currently accessible in the Mendeley catalog.
Full text

AsAP: An Asynchronous Array of Simple Processors

  • Yu Z
  • Meeuwsen M
  • Apperson R
  • Sattari O
  • Lai M
  • Webb J
  • Work E
  • Truong D
  • Mohsenin T
  • Baas B
IEEE Journal of Solid-State Circuits (2008)
  • --

    Readers

    Readers not available. This publication is not currently accessible in the Mendeley catalog.
Full text

Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors

  • Baas B
  • Yu Z
  • Meeuwsen M
  • Sattari O
  • Apperson R
  • Work E
  • Webb J
  • Lai M
  • Gurman D
  • Chen C
  • Cheung J
  • Truong D
  • Mohsenin T
IEEE HotChips Symposium on High-Performance Chips (HotChips 2006) (2006)
  • --

    Readers

    Readers not available. This publication is not currently accessible in the Mendeley catalog.

Professional experience

Research Scientist

Madrigal Elektromotoren GmbH

September 2012

Research Assistant at the VLSI Computation Laboratory

University of California Davis

June 2005 - September 2012 (7 years)

President of the Electrical and Computer Engineering Graduate Student Association

University of California Davis

October 2009 - September 2010 (a year)

Laboratory Manager at the VLSI Computation Laboratory

University of California Davis

January 2008 - May 2010 (2 years)

Chip Packaging and Hardware Test Engineer

University of California Davis

September 2007 - October 2007 (a month)

Manycore (167-core) Platform Lead Architect

University of California Davis

September 2006 - June 2007 (9 months)

Education history

University of California Davis

Ph.D. Candidate in Electrical and Computer Engineering

September 2005 - December 2012 (7 years)

University of California Davis

M.S. in Electrical and Computer Engineering

September 2005 - May 2010 (5 years)

University of California Davis

B.S. in Electrical and Computer Engineering

September 2001 - June 2005 (4 years)