Dean Truong Ph.D., M.S., B.S.

Research Scientist

Madrigal Elektromotoren GmbH

City
San Francisco, California, United States
Discipline
Electrical and Electronic Engineering
Interests
Hierarchical dynamic power management techniques applied to multiple levels of system integration from the processor to cluster levels using LTI control theory and learning heuristics (e.g. fuzzy logic, neural networks, genetic algorithms, etc.).
More... Less...

  • 9 Followers

Stats

About

Natural born U.S. Citizen finishing up a Ph.D. in Electrical and Computer Engineering focusing on the application of dynamic voltage and frequency scaling with a manycore platform architecture for biomedical signal and image processing applications.

Goals/Objective:
To be part of a state-of-the-art research/engineering group in the areas of embedded systems (e.g. real-time communications and multimedia front/back-end), high performance computing (e.g. Exascale computing), and/or biomedical signal, image, and video processing (e.g. medical ultrasound).

Primary Experience:
+ RESEARCH ASSISTANT with 16 authored and co-authored papers in top circuits journals and conferences, including IEEE Journal of Solid State Circuits, VLSI Symposium on Technology and Circuits, IEEE Transactions on Circuits and Systems, HotChips Symposia on High Performance Processors, and ACM/IEEE Design Automation Conference.
+ MANYCORE PLATFORM LEAD ARCHITECT working with a team of 10 M.S. and Ph.D. students on a 167-core globally asynchronous and locally synchronous (GALS) array consisting of 164 DSP processors, three application-specific processors (accelerators), and three 16 KB scratchpad shared memories. Design to tape-out completed in 9 months on 65 nm CMOS. The platform is capable of up to 200 GOPS at nominal Vdd, with peak energy-efficiency at 200 GOPS/W at near-threshold operation.

Specialties:
+ Variation-aware Adaptive and Dynamic Voltage and Frequency Scaling (DVFS) on Manycore Platforms
+ Digital Systems and Computer Architecture
+ RTL Engineer
+ Back-end Design and Verification
+ Digital IC Design
+ Source-synchronous Interconnects
+ Lab Instrumentation & Chip Testing
+ Embedded Software Development
+ LDPC Decoder Architectures
+ Medical Ultrasound Imaging on Massively Parallel Processor Arrays (MPPA)
More... Less...

Publications

  • An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

    Mohsenin T, Truong D, Baas B

    2009 IEEE International Conference on Communications (2009)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • AsAP: An Asynchronous Array of Simple Processors

    Yu Z, Meeuwsen M, Apperson R, Sattari O, Lai M, Webb J et al.

    IEEE Journal of Solid-State Circuits (2008)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • Multi-Split-Row Threshold decoding implementations for LDPC codes

    Mohsenin T, Truong D, Baas B

    2009 IEEE International Symposium on Circuits and Systems (2009)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors

    Baas B, Yu Z, Meeuwsen M, Sattari O, Apperson R, Work E et al.

    IEEE HotChips Symposium on High-Performance Chips (HotChips 2006) (2006)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • Massively parallel processor array for mid-/back-end ultrasound signal processing

    Truong D, Baas B

    2010 Biomedical Circuits and Systems Conference (BioCAS) (2010)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • Circuit modeling for practical many-core architecture design exploration

    Truong D, Baas B

    Proceedings of the 47th Design Automation Conference on - DAC '10 (2010)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network

    Tran A, Truong D, Baas B

    2009 3rd ACM/IEEE International Symposium on Networks-on-Chip (2009)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A 167-Processor Computational Platform in 65 nm CMOS

    Truong D, Cheng W, Mohsenin T, Yu Z, Jacobson A, Landge G et al.

    IEEE Journal of Solid-State Circuits (2009)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A complete real-time 802.11a baseband receiver implemented on an array of programmable processors

    Tran A, Truong D, Baas B

    2008 42nd Asilomar Conference on Signals, Systems and Computers (2008)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

    Truong D, Cheng W, Mohsenin T, Yu Z, Jacobson T, Landge G et al.

    2008 IEEE Symposium on VLSI Circuits (2008)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors

    Tran A, Truong D, Baas B

    2009 IEEE International Symposium on Circuits and Systems (2009)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders

    Mohsenin T, Truong D, Baas B

    IEEE Transactions on Circuits and Systems I: Regular Papers (2010)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • AsAP: A Fine-Grained Many-Core Platform for DSP Applications

    Baas B, Yu Z, Meeuwsen M, Sattari O, Apperson R, Work E et al.

    IEEE Micro (2007)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • The design of a reconfigurable continuous-flow mixed-radix FFT processor

    Jacobson A, Truong D, Baas B

    2009 IEEE International Symposium on Circuits and Systems (2009)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing

    Truong D, Cheng W, Mohsenin T, Jacobson Z, Landge G, Meeuwsen M et al.

    IEEE HotChips Symposium on High-Performance Chips (HotChips 2008) (2008)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.
  • A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms

    Tran A, Truong D, Baas B

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2010)

    • -- Readers Readers not available. This publication is not currently accessible in the Mendeley catalog.

Professional experience

Research Scientist

Madrigal Elektromotoren GmbH

September 2012 - Present

Research Assistant at the VLSI Computation Laboratory

University of California, Davis

June 2005 - September 2012 (7 years 3 months)

President of the Electrical and Computer Engineering Graduate Student Association

University of California, Davis

October 2009 - September 2010 (11 months)

Laboratory Manager at the VLSI Computation Laboratory

University of California, Davis

January 2008 - May 2010 (2 years 4 months)

Chip Packaging and Hardware Test Engineer

University of California, Davis

September 2007 - October 2007 (1 month)

Manycore (167-core) Platform Lead Architect

University of California, Davis

September 2006 - June 2007 (9 months)

Education history

University of California, Davis

Ph.D. Candidate in Electrical and Computer Engineering

September 2005 - December 2012 (7 years 3 months)

University of California, Davis

M.S. in Electrical and Computer Engineering

September 2005 - May 2010 (4 years 8 months)

University of California, Davis

B.S. in Electrical and Computer Engineering

September 2001 - June 2005 (3 years 9 months)