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Michael Shebanow

  • PhD
  • Vice President, R&D Tensilica
  • Cadence Design Systems Inc
  • 10PublicationsNumber of items in Michael's My Publications folder on Mendeley.
  • 3Followers


Michael Shebanow joined NVIDIA in 2003. While at NVIDIA, he has worked on the Tesla product family (G80, GeFroce 68xx series) and was one of the lead architects of the Fermi (GF100) family. Also for Fermi, he managed the shader processor architecture team (covered 5 blocks including the SM & L1). He is currently in the research group investigating next generation graphics and unified programming models for GPUs. Prior to NVIDIA, he has managed the development of a number of processors in multiple architecture families (x86-32, x86-64, SPARC v9, 68k, m88k), and was one of three representatives representing Motorola in the Power PC architecture definition committee. While a graduate student at UC Berkeley, he was one of the original developers of HPS (superscalar, dynamically scheduled processor architectures) (started 1984). Dr. Shebanow holds 25 patents in graphics, processor design, and disk controller areas.

Recent publications

  • Pervasive massively multithreaded GPU processors

    • Shebanow M
  • Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor

    • Simone M
    • Essen A
    • Ike A
    • et al.

Professional experience

Vice President, R&D Tensilica

Cadence Design Systems Inc

September 2017 - Present



UC Berkeley

January 1983 - December 1994(12 years)


UC Berkeley

September 1979 - June 1981(2 years)

Northwestern University

September 1977 - June 1979(2 years)

Followers (3)

Following (6)