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Vikas Shilimkar

  • Ph.D.
  • 11PublicationsNumber of items in Vikas's My Publications folder on Mendeley.
  • 1Followers

Research interests

Signal IntegrityRF/microwaves designPower deliveryInterconnect and passives modelingElectromagneticsDummy Metal FillDC-DC converters

About

I am an RF modeling engineer at Freescale Semiconductor. I received the Ph.D. degree from Oregon State University’s School of Electrical Engineering and Computer Science in Jan. 2014. I received the B.E. degree in electronics and communication from Government College of Engineering, Pune, India, in 2004, and the M.S. degree in electrical and computer engineering from Oregon State University, in 2009. From 2004 to 2007, I was a Hardware Design Engineer with Intel, India, working on motherboard and microprocessor/chipset package design with an emphasis on Power Delivery and Signal Integrity. During the summer and fall of 2010, I was with Intel System Architecture Group, Hillsboro, OR, where I investigated platform power optimization. During the summer of 2012, I was with Intel Signalling team, Hillsboro, OR, where I investigated analytical estimation of eye degradation due to power supply noise. My research interests include electromagnetic analysis, design, and modeling of interconnects and passive components, power/signal integrity analysis of motherboard/package/IC, end-to-end IC power delivery, RF/EM interference, and active-passive circuit co-design.

Followers (1)

Publications (5)

  • Enabling metal-fill-aware design of integrated circuits

    • Shilimkar V
    N/AReaders
    N/ACitations
  • Accurate closed-form capacitance extraction formulas for metal fill in RFICs

    • Gaskill S
    • Shilimkar V
    • Weisshaar A
    N/AReaders
    N/ACitations
    Get full text
  • Experimental characterization of metal fill placement and size impact on spiral inductors

    • Shilimkar V
    • Gaskill S
    • Weisshaar A
    N/AReaders
    N/ACitations
    Get full text
  • Isolation enhancement in integrated circuits using dummy metal fill

    • Gaskill S
    • Shilimkar V
    • Weisshaar A
    N/AReaders
    N/ACitations
    Get full text
  • Noise Suppression in VLSI Circuits Using Dummy Metal Fill

    • Gaskill S
    • Shilimkar V
    • Weisshaar A
    N/AReaders
    N/ACitations
    Get full text

Professional experience

Hardware Design Engineer

Intel Corp

September 2004 - August 2007(3 years)

Education

PhD

Oregon State University

January 2010 - January 2014(4 years)

MS

September 2007 - November 2009(2 years)

College of engineering, Pune, India

BE

June 2001 - July 2004(3 years)