Abstract
An architecture for next-generation memory interface is demonstrated using 90nm bulk silicon to provide a 2-tap emphasized TX with <19ps jitter at 9.6Gb/s. The circuit uses a programmable PLL to track jitter up to 200MHz. The transceiver consumes 100mW from a 1V supply. © 2006 IEEE.
Cite
CITATION STYLE
APA
Prete, E., Scheideler, D., & Sanders, A. (2006). A 100mW 9.6Gb/s transceiver in 90nm CMOS for next-generation memory interfaces. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. https://doi.org/10.1109/isscc.2006.1696055
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