A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS

  • Verbruggen B
  • Craninckx J
  • Kuijk M
 et al. 
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A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm2.

Author-supplied keywords

  • Analog-digital conversion
  • CMOS analog integrated circuits
  • calibration

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  • Bob Verbruggen

  • Jan Craninckx

  • Maarten Kuijk

  • Piet Wambacq

  • Geert Van Der Plas

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