A 400-MT/s 6.4-GB/s multiprocessor bus interface

  • Muljono H
  • Lee B
  • Tian Y
 et al. 
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Abstract

This paper describes the design of a system bus interface for the 130-nm Itanium®2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance.

Author-supplied keywords

  • DLL
  • Edge rate
  • High-speed interface
  • I/O modeling
  • I/O testing
  • Interpolator
  • Package
  • Processor

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Authors

  • Harry Muljono

  • Beom Taek Lee

  • Yanmei Kathy Tian

  • Yanbin Eddie Wang

  • Mubeen Atha

  • Tiffany Huang

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