A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm

  • Yang R
  • Liu S
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A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively

Author-supplied keywords

  • DCC
  • Delay-locked loop (DLL)
  • Edge combine
  • Harmonic lock
  • Successive approximation register (SAR)
  • Variable successive approximation register (VSAR)

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  • Rong Jyi Yang

  • Shen Iuan Liu

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