A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm

  • Yang R
  • Liu S
  • 42


    Mendeley users who have this article in their library.
  • 111


    Citations of this article.


A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively

Author-supplied keywords

  • DCC
  • Delay-locked loop (DLL)
  • Edge combine
  • Harmonic lock
  • Successive approximation register (SAR)
  • Variable successive approximation register (VSAR)

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Get full text


  • Rong Jyi Yang

  • Shen Iuan Liu

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free