Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems

  • Nunez-Yanez J
  • Edwards D
  • Coppola A
  • 4


    Mendeley users who have this article in their library.
  • N/A


    Citations of this article.


An investigation into an effective and low-complexity adaptive routing strategy based on stochastic principles for an asynchronous network-on-chip platform that includes dynamically reconfigurable computing nodes is presented. The approach is compared with classic deterministic routing and it is shown to have good properties in terms of throughput and excellent fault-tolerance capabilities. The challenge of how to deliver reliability is one of the problems that multiprocessor system architects and manufactures will face as feature sizes and voltage supplies shrink and deep-submicron effects reduce the ability to carry out deterministic computing. It is likely that a new type of deep-submicron complex multicore systems will emerge which will be required to deliver high performance within strict energy and area budgets and operate over unreliable silicon. Within this context, the paper studies an on-chip communication infrastructure suitable for these systems.

Author-supplied keywords

  • adaptive routing strategies
  • deep-submicron complex multicore systems
  • deliver reliability
  • deterministic routing
  • dynamically reconfigurable systems
  • fault tolerance
  • fault-tolerant on-chip networks
  • multiprocessing systems
  • multiprocessor system architects
  • network routing
  • network-on-chip
  • reconfigurable architectures
  • stochastic principles

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document


  • J.L. Nunez-Yanez

  • D. Edwards

  • A.M. Coppola

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free