Abstract
This brief deals with the behavior of a dynamic latch used as a voltage comparator. A detailed analysis of the flne settling phase is reported, putting in evidence the non-idealities which lead to comparison errors. A technique to minimize such errors is suggested. An experimental chip has been fabricated and measurements are reported and discussed. © 1998 IEEE.
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CITATION STYLE
APA
Cusinato, P., Bruccoleri, M., Caviglia, D. D., & Valle, M. (1998). Analysis of the behavior of a dynamic latch comparator. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 45(3), 294–298. https://doi.org/10.1109/81.662703
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