Architecture of the scalable communications core's network on chip

  • Ilitzky D
  • Hoffman J
  • Chun A
 et al. 
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Abstract

The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.

Author-supplied keywords

  • Communication
  • Mobile communications
  • Multicore architectures
  • Networking
  • Parallel architectures
  • Parallel processing
  • Wide area networks
  • Wide-area networks
  • Wireless
  • Wireless communications
  • on-chip interconnection networks

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Authors

  • David Arditti Ilitzky

  • Jeffrey D. Hoffman

  • Anthony Chun

  • Brando Perez Esparza

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