Array processors designed with VHDL for solution of linear equation systems implemented in a FPGA

  • Martinez-Alonso R
  • Mino K
  • Torres-Lucio D
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This paper presents a parallel array of processors implemented in
a Field Programmable Gate Array (FPGA) for the solution of linear
equation systems. The solution is performed using the division-free
Gaussian elimination method. This algorithm was implemented in integrated
processors in a FPGA Spartan 3 of Xilinx. A top-down design was used.
The architecture modules were designed in VHDL language and simulated
using the Model Sim 6.3f software. The proposed architecture can
handle IEEE 754 single and double precision floating-point data and
the architecture is implemented in 240 identical processors. Also,
an algorithmic complexity of O(n2) was obtained using a n2 processor
scheme that performs the solution of the linear equations.

Author-supplied keywords

  • FPGA
  • Gaussian elimination method
  • Linear equation systems
  • Parallel processing
  • VHDL

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  • R. Martinez-Alonso

  • K. Mino

  • D. Torres-Lucio

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