Automatic type inference for resynthesis on hardware description languages

  • León G
  • Fabregat G
  • Claver J
  • 2

    Readers

    Mendeley users who have this article in their library.
  • 0

    Citations

    Citations of this article.

Abstract

Reconfigurable architectures are object of many studies that try to find tools for a more efficient way of programming, and friendly for software engineers. In spite of the recent advances, there are some applications in which the generated circuits are quite far from optimal. In this paper, we describe a resynthesis methodology, which is suitable for usual multimedia applications. This method transforms the whole algorithm, written in Small Talk, in a graph of LUTs that implements the required operations without the use of library components. The quality of the obtained circuitry is guaranteed by the use of "type inference", a context dependent technique that is the focus of current research on the design of high level circuit generators. Type inference technique comprises two stages: forward and backward data propagation, which allows a high level resynthesis of the algorithm. Thus, our environment automatically optimizes the word length and size of operators, and reduces their internal data paths and switching activity.

Author-supplied keywords

  • Logic synthesis
  • hardware accelerators
  • object-oriented design
  • re-synthesis
  • reconfigurable hardware tools

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Get full text

Authors

  • José ClaverUniversity of Valencia - Burjassot-Paterna Campus

    Follow
  • Germán León

  • Germán Fabregat

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free