The set of flex-cells, either alone or in combination with standard-cells, provides an optimally tuned set of building blocks for the target IC design, where optimality is measured against accepted and definable (i.e. quantifiable) metrics like clock speed, die size, power consumption, etc.. By allowing the transistor-level structures to be manipulated, flex-cells open up a new dimension in the optimization of automatically created designs. Flex-cells allow both the transistor-level structure and sizing to be manipulated freely. Such flexibility does not come for free, as is to be expected. A host of issues ranging from the correct choice of flex-cell mapping (to transistors) technology, to minimizing the number of flex-cells to be used in a design, to efficient characterization of flex-cells, to the interplay between flex-cell based optimization and other important issues like physical design information, need to be addressed. Preliminary results using flex-cell based optimization suggest that when employed properly, this methodology holds promise of significant benefit to the process of optimizing automatically created digital designs.
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