Crosstalk reduction for VLSI

  • Vittal A
  • Marek-Sadowska M
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The performance of high-speed electronic systems is limited by
interconnect-related failure modes such as coupled noise. We propose new
techniques for alleviating the problems caused by coupling between
signal lines on integrated circuits. We show that models used by
previous work on coupled noise-constrained layout synthesis do not allow
the use of several important degrees of freedom. These degrees of
freedom include the ability to utilize dynamic noise margins rather than
static noise margins, the dependence of coupled noise on drive strength,
and the possibility of using overlaps to reduce susceptibility to noise.
We derive an expression for the coupled noise integral and a bound for
the peak coupled noise voltage which shows order of magnitude
improvements in both accuracy and fidelity compared to the charge
sharing model used in previous work. We use the new bounds to guide a
greedy channel router, which manipulates exact adjacency information at
every stage, allowing it to introduce jogs or doglegs when necessary for
coupled noise reduction. Experimental results indicate that our
algorithm compares favorably to previous work. The coupled noise is
significantly reduced on benchmark instances

Author-supplied keywords

  • Constraint-driven routing
  • Coupled noise
  • Signal integrity

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  • Ashok Vittal

  • Malgorzata Marek-Sadowska

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