The design process of an evolutionary oriented reconfigurable architecture

Abstract

This paper describes the design of a reconfigurable chip programmable at the transistor level and oriented to the implementation of evolvable hardware (EHW) experiments. We tackle the main issues referring to the conception of an evolutionary oriented reconfigurable architecture (EORA): the cell topology; interconnection between cells; transistor sizing; resistor and capacitor implementation in silicon; selection of input and output points; and reconfiguration aspects. A set of evolutionary experiments is described, serving as support for the design choices. Additionally, we propose novel approaches to overcome area requirements for the VLSI design, such as the use of differentiated configurable blocks and a variable interconnection density throughout the chip. © 2000 IEEE.