Direct Digital Frequency Synthesizers With Polynomial Hyperfolding Technique

Abstract

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique. © 2004, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.