FPMR: MapReduce framework on FPGA

  • Shan Y
  • Wang B
  • Yan J
 et al. 
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Abstract

Machine learning and data mining are gaining increasing attentions of the computing society. FPGA provides a highly parallel, low power, and flexible hardware platform for this domain, while the difficulty of programming FPGA greatly limits its prevalence. MapReduce is a parallel programming framework that could easily utilize inherent parallelism in algorithms. In this paper, we describe FPMR, a MapReduce framework on FPGA, which provides programming abstraction, hardware architecture, and basic building blocks to developers.

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Authors

  • Yi Shan

  • Bo Wang

  • Jing Yan

  • Yu Wang

  • Ningyi Xu

  • Huazhong Yang

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