Highly Efficient Entropy Extraction for True Random Number Generators on FPGAs

  • Rozic V
  • Yang B
  • Dehaene W
 et al. 
  • 23

    Readers

    Mendeley users who have this article in their library.
  • 9

    Citations

    Citations of this article.

Abstract

True random number generators are essential components in cryptographic hardware. In this work, a novel entropy extraction method is used to improve throughput of jitter-based true random number generators on FPGA. By utilizing ultra-fast carry-logic primitives available on most commercial FPGAs, we have improved the efficiency of the entropy extraction, thereby increasing the throughput, while maintaining a compact implementation. Design steps and techniques are illustrated on an example of a ring-oscillator based true random number generator on Spartan-6 FPGA. In this design, the required accumulation time is reduced by 3 orders of magnitude compared to the most efficient oscillator-based TRNG on the same FPGA. The presented implementation occupies only 67 slices, achieves a throughput of 14.3 Mbps and it is provided with a formal evaluation of security.

Author-supplied keywords

  • random number generation
  • randomness extraction

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Authors

  • Vladimir Rozic

  • Bohan Yang

  • Wim Dehaene

  • Ingrid Verbauwhede

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free