HOPE: An efficient parallel fault simulator for synchronous sequential circuits

  • Lee H
  • Ha D
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Abstract

HOPE is an efficient parallel fault simulator for synchronous sequential
circuits that employs the parallel version of the single fault propagation
technique. HOPE is based on an earlier fault simulator railed PROOFS,
which employs several heuristics to efficiently drop faults and to
avoid simulation of many inactive faults. In this paper, we propose
three new techniques that substantially speed up parallel fault simulation:
(1) reduction of faults simulated in parallel through mapping nonstem
faults to stem faults, (2) a new fault injection method called functional
fault injection, and (3) a combination of a static fault ordering
method and a dynamic fault ordering method. Based on our experiments,
our fault simulator, HOPE, which incorporates the proposed techniques,
is about 1.6 times faster than PROOFS for 16 benchmark circuits

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Authors

  • Hyung Ki Lee

  • Dong Sam Ha

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