Impact of technology trends on SEU in CMOS SRAMs

  • Dodd P
  • Sexton F
  • Hash G
 et al. 
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Abstract

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-μm radiation-hardened CMOS SRAM is presented

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Authors

  • P E Dodd

  • F W Sexton

  • G L Hash

  • M R Shaneyfelt

  • B L Draper

  • A J Farino

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