Photoresist line edge roughness (LER) has been highlighted to have an adverse impact on device performance whereas post-etch LER is probably the more relevant metric. Post-etch LER can be reduced by migrating to thicker photoresist films or developing etch processes that are accompanied with lower energy ion bombardment. However, the photoresist and etching processes chosen might have desirable attributes and therefore cannot be changed, e.g. large process window or minimal nested-isolated feature etch bias. In this paper, we demonstrate the reduction of LER at the polysilicon gate level by an inexpensive treatment prior to etch. This HBr plasma treatment can be performed in the main etch chamber with minimal impact on wafer throughput. As a result, during the following etch steps, the photoresist mask is more homogeneous from an etch perspective which in turn helps lower the final LER. In addition, results from blanket etch studies on the various photoresist component films are shown. FTIR spectra of unetched and etched films are compared to demonstrate the preferential etching of certain photoresist/polymer components. The large differences observed in the unetched and etched film surface roughness values for certain photoresist components is postulated as an important source of final LER.
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