A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation 2 Sense Amplifier Based Logic 3 Conception of Dynamic Differential Logic

  • Tiri K
  • Verbauwhede I
  • Hall B
 et al. 
  • 33


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This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.

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  • Kris Tiri

  • Ingrid Verbauwhede

  • Boelter Hall

  • P O Box

  • Los Angeles

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