Low power SRAM design using hierarchical divided bit-line approach

  • Karandikar A
  • Parhi K
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This paper presents a novel hierarchical divided bit-line approach for reducing active power in SRAMs by reducing bit-line capacitance. Two or more 6T SRAM cells are combined together to divide the bit-line into several sub bit-lines. These sub bit-lines are again combined to form two or more levels of hierarchy. This division of bit-line into hierarchical sub bit-lines results in reduction of bit-line capacitance, which reduces active power and access time. Optimum values for number of levels of hierarchy and number of blocks combined at each level have been derived. Experimental results show that the observed parameters and estimated ones follow the same trend. It is shown that the reduction in bit-line capacitance reduces active power consumption by 50-60% and the access time by about 20% at the expense of approximately 5% increase in the number of transistors. This approach is further extended by incorporating the controlled voltage swing on bit-lines. This extension reduces the power consumption by another 20-30%

Author-supplied keywords

  • Batteries
  • Capacitance
  • Costs
  • Decoding
  • Energy consumption
  • Integrated circuit packaging
  • Parameter estimation
  • Power systems
  • Random access memory
  • SRAM cells
  • Voltage control
  • active power
  • active power consumption
  • bit-line capacitance
  • hierarchical divided bit-line approach
  • low power SRAM design

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  • A. (Intel) Karandikar

  • K.K. (University of Minnesota) Parhi

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