MARTE based modeling approach for partial dynamic reconfigurable FPGAs

  • Quadri I
  • Meftali S
  • Dekeyser J
  • 6

    Readers

    Mendeley users who have this article in their library.
  • 7

    Citations

    Citations of this article.

Abstract

As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Authors

  • Imran Rafiq Quadri

  • Samy Meftali

  • Jean Luc Dekeyser

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free