Memristor based programmable threshold logic array

  • Rajendran J
  • Manem H
  • Karri R
 et al. 
  • 45

    Readers

    Mendeley users who have this article in their library.
  • 32

    Citations

    Citations of this article.

Abstract

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Authors

  • Garrett RoseThe University of Tennessee

    Follow
  • Jeyavijayan Rajendran

  • Harika Manem

  • Ramesh Karri

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free