MT-ADRES: Multi-threading on coarse-grained reconfigurable architecture

  • Wu K
  • Kanstein A
  • Madsen J
 et al. 
  • 17

    Readers

    Mendeley users who have this article in their library.
  • 9

    Citations

    Citations of this article.

Abstract

The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl’s law, this paper proposes to extend ADRES to MT-ADRES (Multi-Threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.

Author-supplied keywords

  • Methodology
  • Multi-threading

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Get full text

Authors

  • Kehuai Wu

  • Andreas Kanstein

  • Jan Madsen

  • Mladen Berekovic

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free