In this paper new genetic operators are introduced that inherently avoid floating terminals and broken routes while evolving transistor circuits on a CMOS field programmable transistor array (FPTA). They are designed to facilitate understanding and improve transferability of the resulting circuits. Comparators and logic gates (AND, OR, XOR) have been evolved with the proposed algorithm and the results are compared to corresponding experiments that use a straightforward implementation of the genetic operators. Furthermore, netlists are extracted from the evolved circuits and simulated with a SPICE simulator. The simulation results are compared with measurements performed on the chip.
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