An offset cancellation technique for comparators using body-voltage trimming

  • Babayan-Mashhadi S
  • Lotfi R
  • 17


    Mendeley users who have this article in their library.
  • 11


    Citations of this article.


In this paper an offset cancellation technique based on body voltage trimming is presented to be used in the comparators employed in Flash or Successive-Approximation analog-to-digital converters. The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. The technique is employed in the design of a 6-bit 1-GSps Flash ADC in 0.18μm CMOS technology. Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28mV to 750μV operating at 1-GHz with only 25μW power in offset cancellation. The cancellation scheme generally improves the ENOB by approximately 0.5 bit after cancellation.

Author-supplied keywords

  • Body-voltage trimming
  • Clocked dynamic comparator
  • Offset cancellation technique

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Get full text


  • Samaneh Babayan-Mashhadi

  • Reza Lotfi

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free