Post-CMOS processing and 3-D integration based on dry-film lithography

  • Temiz Y
  • Guiducci C
  • Leblebici Y
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This paper presents a chip-level post-complementary metal oxide
semiconductor (CMOS) processing technique for 3-D integration and
through-silicon-via (TSV) fabrication. The proposed technique is based
on dry-film lithography, which is a low-cost and simple alternative to
spin-coated resist. Unlike conventional photolithography methods, the
technique allows resist patterning on very high topography, and
therefore chip-level photolithography can be done without using any
wafer reconstitution approach. Moreover, this paper proposes a via
sidewall passivation method which eliminates dielectric etching at the
bottom of the via and simplifies the whole integration process. In this
paper, two 50-mu m-thick chips were post-processed, aligned, bonded, and
connected by Cu TSVs, which have parylene sidewall passivation.
Daisy-chain resistance measurements show 0.5-Omega resistance on average
for 60-mu m-diameter TSVs, with a yield of more than 99% for 1280 TSVs
from five different chip stacks. Subsequently, the techniques were
applied to CMOS microprocessor stacking as a test vehicle. Die-level
post-CMOS processing for 40-mu m-diameter via etching, redistribution
layer patterning, and chip-to-chip bonding were successfully
demonstrated with the real chips.

Author-supplied keywords

  • 3-D integration
  • Die-level processing
  • Dry-film lithography
  • Parylene bonding
  • Post-complementary metal oxide semiconductor (CMOS) processing
  • Through-silicon via (TSV)
  • Via-last TSV

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