Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best subset among possible redundant architectures. It builds upon the progressive module redundancy technique and the block grading concept. Furthermore, this method is not constrained on TMR but extends to 5MR. Experiment results demonstrate its advantages in efficiency, reliability and cost. The proposed method points out a new direction of economical redundant fault-tolerant designs for nanoelectronics. © 2011 Elsevier Ltd. All rights reserved.
Mendeley saves you time finding and organizing research
Choose a citation style from the tabs below