A reconfigurable FIR filter embedded in a 9b successive approximation ADC

  • Joshua K
  • Lin D
  • Li L
 et al. 
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Abstract

A reconfigurable FIR filter and 9b SAR ADC combination in 0.13 mum CMOS is presented. The filter does not require additional analog circuitry, but is implemented by using the SAR capacitor array with a modified tracking and sampling scheme. The prototype filter-ADC can be digitally configured as a 4-tap filter, as one of two different 12-tap filters, or without any filtering. The prototype occupies an active area of 0.68 mm2, achieves 45 dB SNDR and dissipates 7.3 mW power at 5 MS/s. The lowest frequency notch of the embedded filter attenuates by as much as 30.5 dB in 4-tap mode and 38.4 dB in 12-tap mode.

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Authors

  • Kang Joshua

  • David T. Lin

  • Li Li

  • Michael P. Flynn

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