Reduced complementary dynamic and differential logic: A CMOS logic style for DPA-resistant secure IC design

Abstract

In recent years, Differential Power Analysis (DPA) attack has become a major threat to the security of embedded cryptographic ICs (secure ICs) like smart cards. DPA attack is a powerful side-channel attack. During a DPA attack, the attacker uses power consumption measurements from the secure IC and statistical techniques to correlate the power consumption information leaked with the secret key stored in the secure IC, thus retrieving the secret key, and effectively breaking the secure IC. In this paper, we present a Reduced Complementary Dynamic and Differential Logic (RCDDL) style to design DPA-resistant, secure ICs. RCDDL style ensures that the power consumption of the secure IC remains invariant, and hence, uncorrelated to the input data (secret key). As opposed to existing DDL styles that complement every gate in the uncomplementary logic to generate the differential output, RCDDL style proposes reuse of gates, thus ensuring that a reduced number of gates in the uncomplementary logic are complemented to generate the differential output. Further, we present an analysis of how reduced complementation is achieved while maintaining the capacitance and switching requirements for power invariance. To evaluate the proposed logic style, we built a set of logic gates typically used to design secure ICs. Experiments on a set of circuits, designed using the set of RCDDL gates, show significant improvements in security strength, power consumption and area. © 2008 IEEE.