RRAM motifs for mitigating differential power analysis attacks (DPA)

  • Khedkar G
  • Kudithipudi D
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Hybrid Resistive Random Access Memory (RRAM)/CMOS architectures offer
several opportunities in the next generation high performance systems.
These systems are vulnerable to side channel attacks(SPA), including
Differential Power Analysis (DPA) attacks. An architecture with
crypto-coprocessors integrated on a dedicated CMOS layer and the
associated memory on the RRAM layer, can help mitigate the side channel
attacks on these systems. In particular, we focus on the DPA attacks
which can compromise the system performance, by statistically analyzing
information of intermediate results in a cryptographic computation. In
this paper we propose the use of RRAM to obscure the power signals that
mitigate the DPA attacks. RRAM motifs are dynamically reconfigurable
hardware crossbar structures that can be programmed on-the-fly in to a
memory or sensing elements. We investigate a 4x64 RRAM motif that can
perform memory and sensing in tandem. Our analysis shows that we cannot
easily distinguish between the memory access and sensing operations.
Though the power dissipated in the best and worst case scenarios when
reading from an RRAM motif varied by 9%, it does not provide any
additional information on the specific access. Additionally, it was
observed that the variations in the voltage and temperature of the RRAM
generate noise in guessing the subkey and enhances the DPA resiliency of
the system.

Author-supplied keywords

  • 3D-IC
  • DPA
  • Memristor
  • Power
  • RRAM
  • SCA

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