A Survey on Low-Power Techniques with Emerging Technologies

  • Gaillardon P
  • Beigne E
  • Lesecq S
 et al. 
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Abstract

Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall- around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling. © 2015 ACM.

Author-supplied keywords

  • AVFS
  • DVFS
  • Low-power techniques
  • UTBB FDSOI
  • arithmetic logic
  • power gating
  • vertically stacked nanowires

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Authors

  • Pierre-emmanuel Gaillardon

  • Edith Beigne

  • Suzanne Lesecq

  • Giovanni De Micheli

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