The electrical performance of SiC-based microelectronic devices is strongly affected by the densities of interfacial traps introduced by the chemical and structural changes at the Si O 2 ∕ Si C interface during processing. We analyzed the structure and chemistry of this interface for the thermally grown Si O 2 ∕ 4 H - Si C heterostructure using high-resolution transmission electron microscopy(TEM), Z -contrast scanning TEM, and spatially resolved electron energy-loss spectroscopy. The analyses revealed the presence of distinct layers, several nanometers thick, on each side of the interface; additionally, partial amorphization of the top SiCsurface was observed. These interfacial layers were attributed to the formation of a ternary Si–C–O phase during thermal oxidation.
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