Accurate analysis of the interconnect is imperative in contemporary sub-micron geometry circuits. The drive characteristics of the driving transistor play a significant role in the response of the interconnect. This paper presents a detailed analysis of a capacitively loaded distributed RLC system driven by a transistor. Using an analytic model the performance of the interconnect will be characterized with respect to design and technology parameters of a CMOS process technology with Leff= 0.45 micron.
CITATION STYLE
Patil, R. (1995). Characteristics of interconnect delay in 0.5 micron CMOS. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 17–20). IEEE. https://doi.org/10.1109/asic.1995.580672
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