Design and analysis of low noise amplifier using cadence

Abstract

Low Noise Amplifier also known as LNA is one of the most significant component for application in wireless communication system. It is a very important part in RF receiver because it can reduce noise of gain by the amplifier when the noise of the amplifier is received directly. The low noise amplifier has been designed to get the better performance by follow the requirement in this new era consists of high gain, low noise figure, lower power consumption, small chip area, low cost and good input and output matching. In this research, a LNA schematic consists of three stages which are common gate amplifier, common drain amplifier and active inductor is designed to mitigate this constraint. Common gate and common drain are used for input and output stages in every LNA. Both are also used for excellent input and output matching and have a potential to get a lower noise whereas for active inductor, it is used to obtain the lower power consumption and to reduce the chip size in layout design. The results show that the proposed LNA is able to achieve the best performance with a simulated gain of 14.7dB, extremely lower power consumption of 0.8mW, noise figure of 7dB and small chip area 0.26mm². Consequently, this modified LNA is appropriate for low-voltage applications especially in wireless communication system.