A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

Abstract

For the applications requiring medium-to-high resolution ADCs, the pipelined architecture is considered to be the most optimal structure in terms of power consumption and area. With range overlap and redundant bit at each pipelined stage, the sub-ADC can tolerate large comparator offsets, thereby, leaving the linearity and accuracy requirements for the DAC and the residue gain stage. Typically, the multiplying DAC (MDAC), which is the combination of a DAC and a gain stage, requires a high-gain wide-bandwidth opamp and is the most critical building block. The opamps draw static currents from their power supplies and consume most of the power in a pipelined ADC. Many techniques have been reported to achieve a low-power design by avoiding the high-gain opamp, such as zero-crossing based circuits [1, 2], dynamic source-follower amplification [3], and capacitive charge-pump [4]. These techniques replace the conventional opamps with other low-power dynamic circuits to minimize the static power consumption, but in these alternative structures the conversion gain is not as well-predicted as the opamp-based design. Therefore, additional calibration circuits are typically required to compensate the conversion gain error. Another low-power pipelined ADC is presented in [5] and uses high-performance analog MOS transistors which are not easily obtained in a standard digital CMOS process. ©2010 IEEE.