Fault resilient Galois field multiplier design in emerging technologies

Abstract

Transient error is a critical issue in nano scale devices. The potential replacement technologies for CMOS circuits, such as Carbon Nano-Tube Field Effect Transistor (CNTFET) based circuits and Quantum Cellular Automata (QCA), are further scaled down below 20nm. This results in computations performed in lower energy levels than CMOS, making them more vulnerable to transient errors. This paper therefore investigates the performance of inevitable error mitigating schemes such as the Concurrent Error Detection (CED) over binary Galois Fields (GF) in CNTFETs and QCA. The results are then compared with their CMOS equivalents which are believed to be the first reported attempt to the best of the authors' knowledge. A QCA based GF multiplier layout has been presented as well. The detailed experimental analysis of CMOS with CNTFET design proves that the emerging technologies perform better for error tolerant designs in terms of area, power, and delay as compared to its CMOS equivalent. © 2012 Springer-Verlag.